Motor drives and other forms of power conversion systems convert electrical power from one form to another and may be employed in a variety of applications such as powering an electric motor using power converted from a single or multiphase AC input source, converting AC power from a wind driven generator to supply power to a grid, etc. Power converters may include multiple stages for different types of conversion applications, such as AC/DC/AC drives for electric motors having a pulse width modulated (PWM) active current source rectifier in which AC input power is selectively switched to create a DC output bus voltage from which a load is driven by a PWM controlled inverter stage. This type of converter is particularly useful in driving electric motors in industrial applications requiring variable speed control with varying motor load situations. The inverter typically employs a pair of high/low drivers for each output phase for selectively coupling the output line with one either the upper or lower DC bus line, where semiconductor-based switches such as silicon controlled rectifiers (SCRs), gate turn-off thyristors (GTOs), gate commutated thyristors (GCTs such as integrated gate commutated thyristors (IGCTs) or symmetrical gate commutated thyristors (SGCTs)), etc. are typically used to implement the inverter switching at relatively high frequencies.
Many pulse width modulation schemes for motor drive applications employ minimum dwell and polarity reversal times in the inverter to limit motor peak voltage up to a certain desired value of lead length, where the dwell time describes the minimum time that any switch remains in the on or off state and the polarity reversal time is the minimum time that the output line-line voltage is held at zero when transitioning from positive polarity to negative polarity or vice-versa. A variety of pulse width modulation schemes have been developed to address excessive motor voltages, reflected wave effects, and common mode voltage problems in motor drive converters.
U.S. Pat. No. 7,034,501 to Thunes et al., issued Apr. 25, 2006 and assigned to the assignee of the present application describes spacing modulating signals at low speed to prevent overvoltages through reflected waves in a current regulated drive, in which volt-second distortion is compensated by the current regulator. The entirety of this patent is hereby incorporated by reference as if hilly set forth herein.
U.S. Pat. No. 7,164,254 to Kerkman et al., issued Jan. 16, 2007 and also assigned to the assignee of the present application discloses common mode voltage reduction techniques in which the switching sequence is modified to avoid using the zero vectors so as to reduce common mode voltages in the motor. The entirety of this patent is hereby incorporated by reference as if fully set forth herein.
U.S. Pat. No. 7,106,025 to Yin et al., issued Sep. 12, 2006 and assigned to the assignee of the present application discloses techniques for canceling dead time effects in the algorithm to reduce common mode voltages produced by a three-phase power conversion device in a rectifier/inverter variable frequency drive (VFD), the entirety of which is hereby incorporated by reference as if fully set forth herein.
U.S. Pat. No. 7,034,501 to Thunes et al., issued Apr. 25, 2007 and assigned to the assignee of the present application discloses gate pulse time interval adjustment techniques for mitigating reflected waves in AC motor drives, the entirety of which is hereby incorporated by reference as if fully set forth herein.
Co-pending U.S. patent application Ser. Nos. 12/394,613, filed Feb. 27, 2009, and 12/429,309, filed Apr. 24, 2009, both assigned to the assignee of the present application, both of which are hereby incorporated by reference as if fully set forth herein, disclose controlling common mode voltages in AC motor loads using switching sequences with only active vectors, but this can increase output current distortion, particularly at low speeds and the method may not be easily implemented in all PWM waveform generators.
U.S. Pat. No. 6,819,070 to Kerkman et al., issued Nov. 16, 2004 and assigned to the assignee of the present application discloses inverter switching control techniques to control reflected voltages in AC motor drives, the entirety of which is hereby incorporated by reference as if fully set forth herein. This patent describes method to adjust gate pulses to minimize peak motor over-voltage due to the reflected wave phenomenon. These techniques involve enforcing minimum dwell times and preventing polarity reversal in the line-line voltage applied to the motor by limiting the minimum and maximum value of the duty cycle for each phase independently. When not in pulse-dropping, limiting the maximum and minimum duty cycles of the phases independently enforces dwell time and polarity reversal time in the PWM switching pattern, and peak motor over-voltage is limited when not in pulse dropping. However, the dwell time can be reduced during transition to over-modulation conditions when the modulating waveform of the PWM scheme exceeds the maximum value of the carrier waveform or when the modulating waveform goes below the minimum carrier waveform value, leading to high voltage at the motor terminals. In addition, the polarity reversal time can be reduced during transitions to over-modulation, also causing high motor terminal voltages. Moreover, simultaneous transitions to or from over-modulation on two phases can result in polarity reversals, potentially generating very high voltages (e.g., up to about four times the DC bus level) at the motor terminals, even for short cable lengths. Thus, there is a need for improved inverter pulse width modulation techniques and systems to avoid or mitigate these problems in over-modulation situations.